Semiconductor History | World Trade Center, 8 January 1990 — The Supercomputer Whose Speed Depended on the Compiler
The National September 11 Memorial Museum, Global, Earth · 1990-1
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Semiconductor History | World Trade Center, 8 January 1990 — The Supercomputer Whose Speed Depended on the Compiler
kevin
The open cabinet in this photograph is a 32-node Intel iPSC/860. Each row holds machines built around the processor that Intel hoped would bring supercomputer arithmetic into a single chip.
Intel unveiled the iPSC/860 at New York’s World Trade Center on 8 January 1990. Configurations could connect as many as 128 processing nodes in a hypercube network, with an i860 processor and eight megabytes of memory at each compute node.
The system gave physical form to an unusually ambitious design.
Intel had formally introduced the i860 on 27 February 1989 as its first RISC microprocessor and the first microprocessor to contain one million transistors. Its integer core, floating-point units, graphics logic, caches, and wide internal paths could work in parallel; Intel’s technical paper described an 80-megaflop peak at 40 megahertz for suitable inner loops.
That was the good side of the bet.
Scientific and graphics programs with regular, vector-like work could extract striking performance, and linking many inexpensive processors offered an alternative to buying one highly specialized vector supercomputer. Intel promoted a fully configured iPSC/860 as capable of 7.6 billion floating-point operations per second at roughly one-tenth the price of a Cray Y-MP, and organizations including NASA Ames and Oak Ridge used the systems for real parallel-computing research.
The difficulty was hidden in the phrase “suitable inner loops.”
The i860 exposed much of its pipeline scheduling to software. A compiler had to arrange independent integer and floating-point operations at compile time, even though cache misses, branches, and changing run-time data could invalidate that schedule.
Early evaluators reported only three to four megaflops per node from the available Fortran compiler—far below the architectural peak—and ordinary control-heavy software suffered more than carefully tuned numerical kernels.
Intel improved the compiler and later i860 versions, but the processor never became the general-purpose workstation standard its launch suggested. Its best life was narrower: graphics acceleration and parallel systems such as the iPSC/860 and Paragon.
The machine was therefore both a real achievement and a warning. Hardware can advertise abundant parallel execution, but performance belongs to the full chain from compiler through memory behavior to the program itself.
The pin marks the original World Trade Center complex, where the iPSC/860 was unveiled. That complex was destroyed in 2001; the coordinate identifies the historical site, not a surviving Intel exhibit.
The photographed 32-node machine was documented in 1995 and is an exact member of the announced system family.
Photo: John E. Stone, CC BY-SA 4.0, via Wikimedia Commons.
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