Semiconductor History | Intel Headquarters, 24 August 1998 — Celeron Gets Back the Cache It Needed
· 1998-8
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Semiconductor History | Intel Headquarters, 24 August 1998 — Celeron Gets Back the Cache It Needed
kevin
This exposed 500-megahertz Mendocino die is a later member of the Celeron design that repaired one of Intel’s most conspicuous exercises in product segmentation.
Intel had introduced the original 266- and 300-megahertz Celerons in April and June 1998 for inexpensive PCs. Derived from the Pentium II core but stripped of level-two cache, those “Covington” chips carried the Intel architecture into lower-priced systems at the cost of weak performance in many real applications.
The market noticed the missing cache.
On 24 August 1998, Intel announced 300A- and 333-megahertz Celerons with 128 kilobytes of level-two cache integrated on the processor die. Intel claimed gains of 25 and 38 percent over the cacheless 300-megahertz model in two benchmark suites, while contemporary independent reporting described the earlier products’ price-performance reception as tepid.
Mendocino’s smaller cache was not automatically inferior to the Pentium II’s larger one.
Its 128 kilobytes ran at full processor speed, whereas the Pentium II’s separate 512-kilobyte cache commonly ran at half speed. The result was a cheap processor that performed much closer to Intel’s premium line and, in the 300A’s case, became famous among enthusiasts for often reaching 450 megahertz on a 100-megahertz front-side bus.
That popularity was good for buyers and awkward for Intel.
The redesign delivered credible performance to sub-$1,000 PCs, but it also showed how artificial the first product’s weakness had been. Once cache returned, the budget chip could threaten the price umbrella around the Pentium II, leaving Intel to differentiate products without making the low end unattractive.
The episode is a compact lesson in segmentation.
Removing a feature can create a tidy price ladder on a planning sheet, yet customers compare usefulness rather than organizational intent. Intel recovered quickly because it was willing to reverse the decision within months; Mendocino succeeded by giving the inexpensive product enough of the original design back.
The pin marks Intel’s headquarters in Santa Clara, the dateline of the 24 August announcement. It is the public corporate anchor for this product event, not a claim about a specific launch room; the adjacent Intel Museum is the appropriate visitor setting.
The photograph shows a later 500-megahertz Mendocino rather than either launch model, with its integrated processor die visible.
Photo: cole8888, CC BY-SA 2.0, via Wikimedia Commons.
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