Semiconductor History | Los Angeles Convention Center, 12 August 2008 — Larrabee Tries to Turn x86 Into a Graphics Chip
· 2008-8
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Semiconductor History | Los Angeles Convention Center, 12 August 2008 — Larrabee Tries to Turn x86 Into a Graphics Chip
kevin
On 12 August 2008, Intel researchers presented the architecture of Larrabee at SIGGRAPH in the Los Angeles Convention Center. Intel planned to turn many familiar x86-style cores, wide vector units, coherent caches, and a high-bandwidth ring into a programmable graphics processor.
The proposal challenged the increasingly fixed division between CPUs and GPUs. Instead of depending primarily on specialized graphics pipelines, developers could express rendering and parallel-computing work in software using a general instruction model and tools closer to ordinary CPU programming.
That programmability was the good. Larrabee anticipated a world in which graphics hardware also performed scientific, media, and data-parallel computation, and it forced Intel to develop wide-vector programming, many-core scheduling, cache coherence, and high-bandwidth interconnect expertise.
The ambition also created the problem. A collection of relatively simple x86 cores had to match specialized GPUs in performance, power efficiency, software maturity, drivers, and graphics compatibility at the same time; a flexible architecture was not automatically a competitive product.
Intel still said in September 2009 that products were due the following year. By December, however, the company acknowledged that silicon and software were behind schedule and said the first Larrabee implementation would be used as a software-development platform rather than sold as a standalone discrete graphics card.
The cancellation was a public defeat in a market Intel wanted badly. It showed that the company’s command of x86 CPUs and leading-edge fabrication could not substitute for the specialized architecture, developer ecosystem, and rapid execution already built by established GPU vendors.
The work did not vanish. Concepts and engineering from Larrabee fed Intel’s Many Integrated Core effort and the Xeon Phi accelerator line launched in 2012, giving the failed graphics product an afterlife in high-performance computing.
The cover is a schematic illustration, not a photograph of the SIGGRAPH presentation or a finished retail chip. Its repeated cores and ring make the central bet visible: Intel tried to scale a programmable x86-derived design into graphics, missed the commercial window, and carried part of the experiment into a different market.
Illustration: Tosaka, CC BY-SA 3.0, via Wikimedia Commons
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