Semiconductor History | San Jose McEnery, 19 September 2023 — Meteor Lake Breaks the CPU into Tiles
· 2023-9
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Semiconductor History | San Jose McEnery, 19 September 2023 — Meteor Lake Breaks the CPU into Tiles
kevin
At Intel Innovation in the San Jose McEnery Convention Center on 19 September 2023, Intel detailed the Core Ultra processor then known as Meteor Lake. The mobile chips would become available on 14 December, but the architectural break was already clear: Intel’s client processor was no longer one monolithic die.
The good was modularity. Meteor Lake combined separate compute, graphics, system-on-chip, and input-output tiles on a Foveros base, letting Intel match functions to different manufacturing processes and assemble them into one package.
Its compute tile became Intel’s first high-volume client use of the Intel 4 process, while supporting tiles used external foundry technology. The design also integrated a neural-processing unit for sustained low-power AI work and substantially strengthened the graphics portion of an Intel laptop processor.
This was an important organizational achievement as much as a product feature. Intel had to coordinate internally fabricated and externally sourced silicon, advanced packaging, firmware, operating-system scheduling, and software support so the user experienced one processor rather than a collection of parts.
The bad was that disaggregation did not abolish difficulty; it relocated and multiplied it. More dies and interfaces increased design, validation, assembly, supply-chain, and cost complexity, while every tile still had to arrive in the right quantity and perform within the package’s power and thermal limits.
Independent launch testing also found that the first Core Ultra generation’s graphics and specialized engines were more transformative than its conventional CPU performance. Meteor Lake was a fresh platform foundation, not an across-the-board leap in every benchmark.
The result captured Intel’s manufacturing transition in miniature. Core Ultra showed that Intel could ship a sophisticated tiled consumer processor and use outside process technology pragmatically, but it also made Intel dependent on flawless integration across more boundaries than the old monolithic model required.
This exact pin marks the public convention center where Intel presented the architecture; the venue remains an operating convention facility in downtown San Jose.
Image note: original technical-history illustration created for this memory; it is not a documentary photograph.
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